The present invention relates to a cache memory control unit provided in an information processing apparatus, and, more particularly, to a cache memory control unit which is arranged to improve a throughput if requests from plural instruction processors are required to be processed.
The current large or medium-scale general-purpose computer mainly employs a tightly-coupled multiprocessor arrangement in which plural instruction processors share a main memory. Further, in principle, a main memory has a slower processing speed than an instruction processor. The performance of such a general-computer therefore depends on the throughput of the referencing/writing data operations in the main memory.
As one of the means for solving this short-coming, a system has been proposed in which a cache memory control unit provides a cache memory to be shared by plural instruction processors between the instruction processor and the main memory. U.S. Pat. No. 5,070,444 discloses a device in which a cache memory address section is divided into plural banks so that each bank receives the corresponding requests if plural instruction processors request to access their corresponding banks. This device, hence, is capable of processing the requests from the plural instruction processors in parallel.
Generally, a cache storage CS5 contained in the cache control unit 3 is formed on a different implemented module from the address array 4. The time duration for reading the cache storage CS will be longer them the request cycle time of accessing data in the instruction processor.
The conventional cache memory control unit does not take into consideration a shortcoming that a reading request interval of a cache memory or a cache storage CS is longer than one machine cycle. That is, if the reading cycle of the cache storage CS is longer than one data access request cycle of an instruction processor, for example, if the instruction processor needs two cycles (FIG. 3A), the request of the instruction processor is made to required to wait at the receiving stage in the cache memory control unit.
The data processing apparatus disclosed in the foregoing US prior art is capable of receiving each request from plural instruction processors at the corresponding bank. But if the previously received request occupies the bank, the subsequent request has to wait at the directory section.